The present invention generally relates to semiconductor input protection devices. More specifically, the invention relates to electrostatic discharge protection of input terminals of a semiconductor device.
As semiconductor technologies continue to decrease in size between technological generations, electrical issues due to high-voltage events become more significant. Small device feature sizes mean that problems such as meeting required spacing for device isolation and the effects of parasitic lateral bipolar devices within diffused wells become more of a concern. Low doping levels in wells and epitaxial layers commensurate with small feature size technologies are beneficial for low source-drain capacitance but aggravate the ability to withstand overvoltage events. Both the effects of scaling and certain artifacts of processes optimized for small feature sizes affect devices designed to protect against high-voltage events.
The use of typical CMOS field effect transistors (FETs) in input protection devices has many drawbacks. These devices are subject to degradation or complete breakdown in the presence of the high current density and electric fields encountered during ESD events. Additionally, use of typical CMOS FET devices introduces parasitic structures that in turn provide unwanted current paths. These unwanted current paths may short out the entire device (a phenomenon known as latchup). Parasitic pnpn and bipolar devices are typically formed as the result of CMOS processing steps and applied voltages.
One drawback of a parasitic pnpn device is that the structure has multiple stable current conduction states. For relatively low voltages, a stable high impedance region of operation exists and is commonly known as a blocking state (an OFF state). The blocking state is characterized by a high impedance across the pnpn structure. As the voltage across the pnpn structure increases a voltage referred to as a snapback voltage (Vs) is reached. At the snapback voltage a transition to a second state, known as the latched state (or ON state) is possible. The latched state is characterized by a low impedance and causes a highly conductive path to form. This paths may conduct enough current to disable or destroy a semiconductor device. Once triggered in semiconductor structures, the latched state may not be switched off without removing the source of power to the device.
In conventional integrated circuits input protection diodes 100 are typically arranged as shown in FIGS. 1A and 1B. Generally this type of arrangement of diodes avoids formation of the parasitic devices mentioned above. Input terminals V+ and V− represent connections for applying a differential signal pair. Input terminal V+ connects to diode stack 105. Diode stack 105 includes two diodes connected back-to-back at their respective cathode terminals. Diode stack 115 connects in series with diode stack 105. Diode stack 115 includes diodes connected back-to-back like the arrangement of diode stack 105. Diode stack 115 is also connected to ground. Referring to FIG. 1B, input terminal V− and a second ground are applied between diode stacks 110 and 120.
Typically, electrostatic discharge (ESD) protection devices have scaled in size in proportion to a magnitude of protection voltage desired. In addition to size constraints due to scaling, a dedicated discharge path to ground for individual input pins has been used. A dedicated discharge path per input pin further exacerbates the size problem coming from the scaling requirement since the entirety of each input pin protection device scales by the same factor. Additionally, for ESD protection in semiconductor circuits, where protection capabilities on the order of, for example, 15 kV are required, conventional protection devices, such as CMOS transistors, may not be effective and may further damage the protection devices.